1. Technical Field
The field of the invention is that of forming shallow trench isolation structures (STI) separating components of an integrated circuit with insulating films that are deposited in shallow trenches.
2. Background of the Invention
In recent years, the LOCOS method of forming isolation structures has given way to a shallow trench isolation method in which a trench is etched directionally into the semiconductor substrate.
The etching process permits much better control of the lateral extent of the structure than was possible with the LOCOS method, since the oxygen used in the oxidizing step diffused laterally and extended outward from the aperture in the hard mask defining the intended extent of the isolation structure.
The trench isolation process conventionally uses chemical-mechanical polishing (CMP) in which an abrasive removes excess trench fill material to establish a planar surface.
A drawback of this approach is that the CMP process produces scratches or chatter marks in the surface that may contribute to the total number of defects.
In current technology, one of the highest yield detractors in front end processing is CMP-induced defects.
Typical “fixed abrasive” CMP processes leave a high density of scratches. Slurry CMP produces “dishing” or local nonuniformity in wide isolation areas.
In addition, scratches may be filled with insulator or conductor, both of which can cause device failure or inconsistent performance.
The mechanical abrasive process tends to produce substantial variation in planarity over the wafer surface.
In addition, the equipment required and consumables for the process, such as slurry and abrasive pads, contribute to the cost of chips fabricated using this technique.
U.S. Pat. No. 6,001,696 shows a method of filling isolation apertures completely up to the top of a thick lift-off layer, with the result that there is a tall projection stub on the top of the isolation members, extending to a considerable distance above the device layer that may interfere with the lowest level of interconnect, such as a polysilicon local interconnect.
The semiconductor industry could benefit from a technique that produces acceptable planarity without the defects, extra equipment, consumable cost, and cycle time associated with the CMP process.